Aditya Naik
Software Engineer, SiFive
The talk
Chisel: The Next Generation
Chisel is a Scala-embedded DSL for describing hardware. Created by UC Berkeley researchers in the early 2010s, Chisel has undergone numerous iterations and is now used heavily by many modern hardware companies, including SiFive, where it forms the backbone of highly parameterized RISC-V CPU generators.
We have been undertaking a multiyear effort of migrating Chisel and our internal SiFive codebases to Scala 3. This talk will highlight the techniques, pitfalls and takeaways from our large migration from Scala 2 to 3. I’ll also touch upon the new features we’re excited about in Scala 3 and how we’re planning on incorporating them in Chisel.
About Aditya
I’m a software engineer at SiFive on the Platform Technologies team where I work on
Chisel, LLVM CIRCT and other technologies that form the core platform for SiFive’s
RISC-V hardware generators. I previously worked on the MicroPython language for
memory-constrained embedded systems. I’m interested in the intersection of languages,
hardware and programming paradigms – specifically how modern programming paradigms
impact the implementation of new languages.